The present invention relates to the hardware devices used to release the microprocessors of the switching nodes in a data transmission network from making statistics on incoming or outgoing frames and in a general way on routed, broadcast, stored or forwarded datagrams, and relates particularly to a memory statistic counter able to count the accesses to a zone of a memory.
With the increase in use of computing facilities throughout modern society, and in particular with increased communication over modern networks having higher transmission speeds than previous conductive wire connections, there is a substantial interest in new methods of communication integrating voice, data and images particularly for so-called multimedia applications.
In modern transmission networks, users typically will agree with a service provider to provide a certain quality of service involving, for example, pre-agreed limitations on the cell error ratio, that is the number of cells including errors that can be tolerated for a given number of cells transmitted, the cell loss ratio, that is the number of cells that the network may lose for a given number of cells transmitted as is typically due to oversubscription and other causes.
The service parameters are agreed upon depending on the anticipated traffic. For example, voice and video communications typically can be effectuated allowing rather higher bit error rates than data communications. However, voice and video are more sensitive to variation in cell delay than are data communications. Accordingly, these and other parameters must be measured in use to ensure that the service contracted for is met by both user and service provider.
In order to control the flow of traffic and maximize the utilization of network resources, it is important to determine whether these parameters are met by both user and service provider. In order to assure compliance, the traffic source node must apply the traffic contract parameters to a  less than  less than traffic shaping greater than  greater than  circuit which limits the transmission of user cells in accordance with the specified parameters. Similarly, within the entrance node of the wide area network, the service provider may implement a  less than  less than traffic policing greater than  greater than  circuit which limits the frequency and burst size of user cell transmission increasing the cell loss priority or discarding cells that exceed the limits (so-called nonconforming cells), as specified by the traffic contract parameters.
It is desirable to measure specific statistics of the network""s operation such as the frequency of occurrence of various types of cells in order to optimize network utilization. For example, the cell headers include indications of cell loss priority which can be raised by the network when a user exceeds the parameters of the corresponding traffic contract. The frequency of occurrence of high cell loss priority indication can accordingly be monitored to ensure that the network is not being over utilized.
A device solving the above problem is described in U.S. Pat. No. 5,761,191. This device is a test instrument comprising a content addressable memory for identifying cells belonging to specific virtual connections or for identifying OAM (operations, administration and maintenance) cells by examining the headers of all cells transiting a node. A microprogram within a microsequencer is vectored responsive to each cell type for updating appropriate statistical counters. Although such an instrument is very useful to collect important statistics for test and measurement of the operation in an asynchronous transfer mode (ATM) communication network, it uses a microsequencer to speed up processing normally made by a processor and retains a classical dual port memory which needs an external incrementer (counter/adder) used for each counting request requiring a read plus a write to the memory.
Accordingly, an object of the invention is to provide a hardware counting device for establishing statistics on incoming and outgoing data frames in a transmission network thus negating the need for a microsequencer, and an external incrementer.
Another object of the invention is to provide a hardware counter for counting the number of accesses to a preprogrammed memory by a microprocessor.
These and other objects are realized by a memory statistic counter for counting the number of accesses by a microprocessor to at least a portion of a memory the portion of memory in response to control signals from the microprocessor, adding logic means comprising a first register which is incremented each time the portion of memory is accessed by the microprocessor and providing a registration signal when the number of accesses is equal to a predetermined numbers and queuing means for registering a value in a registering memory in response to the registration signal and providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined number of accesses to the portion of memory have occurred.
Another aspect of the invention is a memory statistic system comprising a memory statistic counter as defined above and including a programmable time counter using one of the adding logic means in which a register is incremented when a time signal is provided by the microprocessor and a registration signal is provided when the number of occurrences of time signals is equal to a predetermined number, queuing means registering a predefined value in the registering memory in response to the registration signal and for providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined period of time has lapsed.